Many memory devices have both an active and standby mode. In an active mode, storage locations can be accessed according to a particular operation (e.g., read, write, program, erase, etc.). In a standby state, storage locations are typically not accessed, and a memory device retains the data values stored within.
While it remains a continuing goal to reduce overall power consumption in memory devices, low power consumption can be a particularly important feature in limited power systems (e.g., battery powered devices). Such a need has given rise to low power memory devices, sometimes referred to as “micropower” or more battery life memory devices (including MoBL™ memory devices manufactured by Cypress Semiconductor Corporation of San Jose, Calif.).
The particular memory cells formed within a low power memory device can have various configurations, including one-transistor cell (e.g., dynamic random access memory (DRAM), or “pseudo” static RAMs (PSRAMs)). However, static RAM (SRAM) type memory cells can provide rapid performance, and in some configurations, can draw a favorably low stand-by current. More particularly, a six-transistor type SRAM type cell can draw relatively small amounts of current.
However, because of leakage current, a memory cell must typically draw some minimum current (referred to herein as a minimum data retention current) in order to retain a data value. Therefore, in a standby mode, a block of memory cells can have a minimum current draw necessary to retain stored data values.
Various approaches have been proposed for reducing power consumption in various types of semiconductor devices. A first conventional approach includes limiting a voltage provided to a block of memory cells (voltage control). As will be described below, while such an approach may be adequate for larger sized technologies and forgiving standby current values, such approaches may not be sufficient for smaller sized technologies and more stringent standby current specifications.
A second conventional approach includes threshold voltage (Vth) “hopping”. In such an approach, when a circuit undergoes increased activity, a back-gate bias can be lower, decreasing the threshold voltages of transistors. Conversely, when the circuit is less active, a back-gate bias can be increased, providing higher threshold voltages for the transistors.
A drawback to such a conventional approach can be the additional circuits (e.g., charge pumps and the like) that may be necessary to generate the back-gate bias.
A third conventional approach includes a “gated-ground” for sections of a memory circuit. In particular, blocks of memory cells can be commonly connected to a “virtual” ground. The virtual ground, in turn, can be connected to the true ground by a “gating” n-channel transistor. When a block of memory cells is in a data-retention mode, the corresponding gating transistor is turned off.
A drawback to such a conventional approach can be data retention. Because a virtual ground is floating, eventually the necessary minimum data retention current for memory cells may no longer be present. This can result in loss/corruption of stored data values.
Other conventional approaches utilize more complicated manufacturing technologies, such as dual/multiple threshold devices. In such approaches selected transistors (e.g., those in certain current paths) are manufactured to have higher threshold voltages than others.
A drawback to such an approach can be the added complexity and/or cost necessary to provide such different threshold voltages.
Other conventional arrangements can include utilizing dual power supplies “dual-VDD” or dynamically boosting power supplies “VDD hopping”. Both cases are aimed primarily at reducing the active current drawn by providing a high voltage to an active portion of the device, while providing a low voltage to inactive portions of the device. VDD hopping can have the same drawback as Vth hopping: the need for charge pump circuits, or the like.
While the above conventional approaches may provide adequate standby current values for certain manufacturing technologies, these approaches may not be suitable for more advanced technologies. In particular, as minimum transistor size capabilities increase, resulting leakage currents rise. Even more particularly, in metal-oxide-semiconductor (MOS) type integrated circuits, at gate sizes of 0.25 μm or even 0.16 μm voltage control techniques (e.g., maintaining a given voltage to a block of memory cells) may control leakage currents fairly well.
However, as manufacturing technologies migrate to smaller sized devices (e.g., 0.13 μm, 0.10 μm and below), such voltage control approaches can fail to meet more stringent lower power (e.g., low standby current) specifications. It is noted such higher standby current values typically arise from uncontrollable process variations, such as the dimensions of gate lengths (e.g., polysilicon pattern critical dimensions) and or threshold voltage mismatches within a memory cell.
In light of the above, it would be desirable to arrive at some way of reducing standby leakage current in a memory device without incurring the drawbacks of conventional approaches, like those noted above.